EE287- Tutorial on Timing logic
• How to time logic?
• Underlying equations
• Methods used
• Why these are used?
• Assumptions made
• Worked example consisting of at least 3 gates
• Pictures, tables and graphs if required.
1. CLOCK:
Being students of Electrical Engineering, clock plays a vital role in our digital world. By mentioning clock, I mean “digital clock signal” (clk). It is basically a voltage signal which is similar to a square wave that consists of two voltage levels: High (varies with circuit necessaries) and Low (0).
It is represented as follows: Many electronic circuits don’t find the requirement of the clock. Such circuits just calculate the Tp (Propagation Delay) to occur at the final stage output. Whereas, we deal with
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a. Setup time:
Assume an input to the D flip-flop. This input might as well vary anytime. Now let us introduce a positive edge triggered clock. Now to see the setup time, we need to check some part of the D input before the edge of the clock could occur. So basically, Setup time is defined as the minimum amount of time the data signal is held stable before the clock event. By this the data can be sampled properly.
Now let us understand why the set up time arise?
Every circuit has an input and output capacitance. The applied voltage at the input charges the input capacitor. The circuit sees the charge on capacitor at the input. This charging and discharging of capacitor takes some finite time. By this we need to setup the data in accordance with the clock.
b. Hold Time:
For the hold time, the clock samples the data arriving after it has occurred. So the clock samples data for some finite period and also checks for the stable data. So basically, Hold time is defined as the minimum amount of time for which the data is held stable after the clock event.
Why hold time
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These work synchronously. Synchronous means, that the same clock is fed to all the flip-flops. It is the maximum difference in the time of arrival of one clock signal to reach the consecutive storage elements. This difference is due to variations while the clock is been arrived at the next register. These violations normally occur due to the buffers present so that proper delays at each outputs are met. These violations are termed as “skews”. There are two types of skews namely positive and negative skew. For this we introduce two named clocks: Launch and Capture Clock. As the name indicates, Capture clock is the edge at which the data is detected and Launch clock is the edge at which the data is been launched in the earlier register that is supposed to be captures at the current
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Weng, S. H., Kuo, Y. M., & Chang, S. C. (2012). Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic. ACM Transactions on Design Automation of Electronic Systems (TODAES), 17(2), 16.
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