Low-Voltage Current-Mode Realization of Digital Logic Gates using CMOS
In this paper a new technique is introduced for implementing the basic logic function by using analog current-mode techniques. By expanding the logic function in power series expression, and using adder and sub-tractor realization of the basic logic function is simplified. To illustrate the proposed technique, a CMOS circuit for simultaneous realization of the logic function NOT, AND, OR, NAND and XOR is considered. PSPICE simulation results, obtained with ±2V supply, are included.
Key Word: Current Mirror; CMOS analog multiplier; Current mode; Translinear principle; Digital logic circuits;
INTRODUCTION
The current-mode implementation of logic gates is a very important for current mode analog signal processing system. Mixed analog/digital electronic circuits are becoming increasingly important. Digital electronic circuits are mostly designed in CMOS technology. To be able to integrate the digital and analog parts on to one chip, high performance analog CMOS circuits are required (Ismail and Fiez, 1994) and a large number of mixed analog/digital VLSI integrated circuits realized in state-of-the-art digital CMOS technologies are now available (Laker and Sansen, 1994).
In fact the emergence of ICs incorporating mixed analog and digital functions on a single chip has led to an advanced level of analog design (Toumazou et al., 1990). Of particular interest here is the current-mode approach for designing analog ICs. It is well known that current-mode analog signal processing offers some important speed advantages over the traditional voltage-mode signal processing (Allen, 1990). At present current-mode implementations are available for a wide range of analog elect...
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...t, context switch and effects of various history register lengths- due to the increasing interference in the branch history the IHRT scheme performs the best and according to the simulations, it is evident that increasing the history register length often improves the prediction accuracy and effect of context switch- uses the BHT to keep track of branch history, the table needs to be flushed during a context switch are portrayed. On comparison, best predictors gave 94.4% accuracy whereas two-level predictors pushed it to 97%, the other 3% was still substantial miss rate and current version of simple scalar gives 98.8% hit rate.
Reliability is one of the most important factors in circuit design. For modern CMOS technology, the circuit reliability is influenced by the shrinking of technology, the reduced supply voltage, higher frequency, and higher circuit density. These factors affects the circuit's probability of soft errors (also called single event upset). In addition, the process variation introduced in the fabrication process is also a big challenge for circuit designers because it makes the same circuit show different characteristics. Moreover, to reduce power consumption of the circuit, the method of reducing supply voltage to near threshold region is used, which is anticipated to have more effects on the reliability of the circuit.
...ifficult. Consequently, if logic blocks are statically determined to be operating at low or high VDD, the placement and routing algorithms need to be modified accordingly as in [11]. However, static assignment of VDD to the blocks may prevent the ability to reduce power consumption or to meet timing constraints for some designs. In contrast, the use of VDD-programmability for each block helps to tune the number of high and low VDD blocks as desired by the application. In this approach, the challenge is in determining the VDD assignments to each block. The need for level converters wherever an low-VDD logic block drives an high-VDD block and the associated delay and energy overheads are an important consideration when performing these VDD assignments. Furthermore, positioning of the level converters influences the ability to assign lower VDD’s to the routing blocks.
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This proposed multiplier uses a reduction format with predetermined stage heights for having quick results and further minimum power delay product (PDP).When the Simulation results were performed using HSPICE at 0.18µm CMOS technology, the 8x8 multiplier shows optimal speed performance against basic Dadda Tree multiplier and Wallace Tree Multiplier implemented with and without 4-2 Compressors with minimal transistor count and PDP. This proposed reduction format can also be applied to higher order NxN multipliers for high speed
Instead of Carry Look ahead adder other multipliers can be used and the work can be extended by using this multiplier in the alu, accumulator unit design and compare the result with the existing design.
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