Advantage And Disadvantage Of Multiplier

1937 Words4 Pages

1.Introduction
Multipliers plays the major role in today’s digital processing technology and various other applications. With advances in technology, many researches have tried and are trying to design multipliers which offers the following design targets such as- speed, power consumptions, regularity of layout and hence less area or even combination of them in one multiplier and making them suitable for high speed, low power, and compact VLSI design. Vedic Mathematics is used to reduce the delay and to give high speed multiplier.
2. Vedic Multiplication
2.1 Vedic Algorithm Among the 16 sutras of the ancient Indian Vedic Multiplication, Urdhava Tiryakbhyam was one of the sutras that is used in this Vedic Multiplier Module design in order …show more content…

Though both multiplier have the same number of multiplication, array multiplier uses some blocks like shift and add for designing higher order multiplier. Vedic Multiplier Module is designed using cadence software, as it was more effective way of building the blocks in the silicon chip.[2]
4.1 Vedic Multiplier Module Module design for 2*2 bit Module The schematic block design for 2*2 bit module was explained below Fig .1. which was build using one bit multipliers and adders. For the design of one bit adder and multiplier, two input AND gate and full adder is used respectively.[3] Fig.1 Vedic Multiplier Module block diagram for 2*2 bit
Consider a two data input each of length 2 bits; say A1 A0 and B1 B0. Therefore the output bit is of four bit long, say as C2 S2S1 S0. The block diagram for the 2*2 bit module is shown in Fig .2. In 2*2 Vedic Multiplier Module Module S0 is obtained by multiplying the terms A0 & B0 vertically. Similarly S1 is obtained by crosswise addition of A1B0 &A0B1 and carry from the previous addition during S0 . S2 bit is obtained by the vertical addition of bits A1 B1 terms with the carry generated from the previous addition S1. C2 is nothing but the carry produced from the addition of …show more content…

Conclusion This paper presents a highly effectual method of Multiplier design-Urdhva Triyakbhyam based on the Vedic Multiplier Module method and it shows the computational advantage over other methods and hence delay calculated using this method is found to be more efficient than other conventional method .

7. Future scope Instead of Carry Look ahead adder other multipliers can be used and the work can be extended by using this multiplier in the alu, accumulator unit design and compare the result with the existing design.
8. Reference
[1]Jagadguru Swami, “Vedic Mathematics or Sixteen Simple Mathematical Formulae from the Veda, Delhi (1965)”, Varanasi, India, 1986.
[2]Pushpalata Verma, K. K. Mehta “Implementation of an Efficient Multiplier based on Vedic Mathematics Using EDA Tool,” International Journal of Engineering and Advanced

Open Document