Analysis Of Dadda Tree Multiplier

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3.2 Dadda Tree Multiplier Dadda proposed an algorithm with predetermined sequence of matrix (stage) heights for NxN multipliers to have reduced number of reduction stages. It is developed by working back from two row stage. The height of each intermediate stage is limited to floor value of 1.5 times the height of the successor stage [9]. i.e., Height of stage i = (3/2) * Height of stage i+1. Then sequence of stage heights are 2,3,4,6,9,13... Figure 5: 8x8 Dadda Tree Multiplier The 8x8 Dadda tree multiplier at 5 stages is shown in Figure 5. The recursive algorithm used in partial product reduction of a Dadda Multiplier (here 8x8) is as follows, The maximum height of an 8x8 multiplier is 8 bits. The next stage height should be 6, so after …show more content…

Multipliers built from 4-2 Compressors Compressors when used in partial product reduction phase in multipliers will help in having lesser number of interconnections and adder cells. As 4-2 compressor has less delay compared to two full adders; in high speed multipliers, using compressors instead of conventional adders lead to fast output generation and also the number of reduction stages gets reduced. The 4-2 compressor shown in Figure 3 is better suitable in Multiplier’s design as it requires lesser transistor count and it provides better performance. 4.1 Wallace Tree Multiplier using 4-2 Compressors 8x8 Wallace Multiplier using 4-2 compressors (rounded rectangles) is shown in Figure 6. On using compressors the number of reduction stages gets reduced to 3, instead of 5 stages when only half and full adders are used. The delay and thus PDP also gets reduced. The Multiplier uses 17 no. of 4-2 Compressors, 18 full adders and 9 half adders. This Wallace tree has lesser delay compared to the one which does not use 4-2 compressors. Figure 6: 8x8 Wallace Tree Multiplier using 4-2 …show more content…

This proposed multiplier uses a reduction format with predetermined stage heights for having quick results and further minimum power delay product (PDP).When the Simulation results were performed using HSPICE at 0.18µm CMOS technology, the 8x8 multiplier shows optimal speed performance against basic Dadda Tree multiplier and Wallace Tree Multiplier implemented with and without 4-2 Compressors with minimal transistor count and PDP. This proposed reduction format can also be applied to higher order NxN multipliers for high speed

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