Essay On Cache Coherence Protocols

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Literature Review On Cache Coherence Protocols
Shared memory multiprocessors provide the advantage of sharing code and data structures among the processors comprising the parallel application. As a result of sharing, multiple copies of the shared block exist in one or more caches at the same time. The copies of the shared block existing in different aches must be consistent.t. This is called as the cache coherence problem.
Various protocols have been designed to ensure coherence in hardware and policies made to prevent the existence of shared writable data in more than one cache at the same time.

The Hardware cache coherent protocols include snoopy cache coherence protocols, directory cache coherence protocols and cache-coherent network architectures.

1.Snoopy Cache Coherence Protocols

Snoopy cache coherence protocols are best suited for bus-based, shared memory
Multiprocessors as they take make use of the broadcast capability of the single interconnect. The snoopy cache coherence protocols can be divided into two main categories
Write Invalidate and Write Update.

1.1 Write Invalidate Protocols
In Write Invalidate protocols, the processor that modifies a block of shared data invalidates all other copies of that shared data in other caches and then updates its own without further bus operations. There are four protocols that fall under this category:

1.1.1 Goodman Protocol
This protocol was proposed by Goodman in 1983 and was the first write-invalidate protocol. It is also known as Write-once protocol.
This protocol associates a state with each cached copy of shared data block. The different states that can be associated with the block are as follows:
• VALID: The copy of block is consistent with the memory copy.
• INVALID: T...

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...Cache Coherence Protocol
2.3 Chained Directories Cache-Coherence Protocol
It keeps track of the shared copies of data by maintaining a chain of directory pointers hence called chained directories protocol.
Fig. Chained Directories Cache Coherence Protocol
Suppose that there are no shared copies of location X. If processor P1 reads location X the memory sends a copy together with a chain termination (CT) and keeps a pointer to P1. Subsequently, when processor P2 reads location X, the memory sends a copy to the cache of processor P2 along with a pointer to the cache of processor P1. If processor P3 writes to location X, it is necessary to send a data invalidation message down the chain. To ensure sequential consistency, the memory module denies processor P3 write permission until the processor with the chain termination acknowledges the invalidation of the chain.

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