Multiplier Essay

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2.1 LITERATURE REVIEW ON MULTIPLIERS
Multiplier is key fundamental component for many high performance systems such as FIR-filters, microprocessors, digital processors, multimedia applications etc. Multiplier plays main role in system performance [3] [4] [5] because multiplier is generally the slowest element in the system. Furthermore, it occupied a large silicon area. Hence, optimizing speed and area are major design issues however area and speed both are conflicting performance constraints’.
There we are talking about digital multiplier which multiplies two binary numbers, because In new age where digital systems are capturing market at the place of analog systems thus for processing data and for many other requirements there is a huge demand for high speed low area as well as low power consuming multiplier. Multiplier is the slowest and more area consuming part in any system thus for performing multiplication, we do not have any direct tool. We have used adders for implementation of multiplier which made any multiplier slow and biggest part of any processor or ALU.
There is a previously we have make a start both these algorithms then there came further modification for them are as array multiplier and parallel multiplier then these all have became more enhance and there came other algorithms. There multiplier can be divided on various types on the basis of data processing they are classified as serial multiplier parallel multiplier and serial-parallel multiplier .In parallel multipliers, there are two main classifications. They are array and tree multipliers. C.S. Wallace proposed a tree multiplier architecture which performs high speed multiplication. Baugh-Woolley multiplier [6, 18] is also an array multiplier but can perfo...

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...mpared to Booth encoded radix-4 multiplier [7].
First, they extended GF-ACG to describe any GF based on NB in addition to polynomial basis (PB). We then presented a formal design of Massey-Omura parallel multipliers using the extended GF-ACG and showed that the verification time was greatly reduced as compared with that of the conventional methods. For example, a multiplier over GF (264) was verified within 7 minutes. As a further application, we designed the exponentiation circuits based NB and evaluate the performance in comparison with that of the corresponding PB-based circuits. The proposed method is applicable for both binary and multiple-valued implementations since the GF-ACG description is technology-independent except for the lowest-level description. The formal design of GF arithmetic circuits based on both PB and NB would remain in the future study [9].

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