Design and Implementation of Multi-channel ADPCM CODEC

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III. ARCHITECTURE IMPLEMENTATION
Based on implementation of FMULT_ACCUM and control unit, this system was implemented in three different types. Bit serial, pipeline and single resource. This paper discusses the design and implementation of bit serial architecture. The main motive behind bit serial implementation was to reduce the area and cost at the expense of speed.

Figure 2. FMULT_ACCUM Implementation
Figure 2 shows the implementation of FMULT_ACCUM. Inputs to the FMULT block are two’s complement and floating point parallel input. Output of this block is two’s complement 1 bit serial output. A four bit Count_in signal is used as a counter which avails FMULT to repeat operations after 16 iterations. Clear_Accum and Clear_Carry signals are used to reset accumulator. Done_Signal is used to reset the counter. The reason to choose 146 will be discussed in the accumulator section. These logics are implemented using finite state machine.
A. FMULT
The operation of FMULT is as follows. First, the two’s complement input is converted to floating input. The mantissa of each signal is multiplied, and exponent and sign bit are added to obtain the floating point output. This is then converted to two’s complement parallel output. Input to the accumulator is one bit serial. Hence the parallel output in FMULT is converted to serial output by loading it into a shift register and then shifting it out serially.
The allocation of 16 clock cycles for FMULT is shown in Table 1. At 0th clock cycles, the channel will be selected and everything will be reset. In the first clock cycle, the signal An and SR will be loaded. Later, mantissa multiplication takes place from 2nd to 9th clock cycles; exponent addition takes place from 2nd to 7th clock cycles...

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.... This is implemented using finite state machine. Initially, the control unit is stalled for arbitrary time i.e. 16 clock cycles. Thereafter, the start signal goes high and starts the FMULT_ACCUM module. From the previous section, it is seen that the FMULT_ACCUM takes 146 clock cycles to complete. After completion done signal is generated and fed to the control unit. Then arbitrary period of 16 clock cycles is waited and then write signal is given to register and the results are latched to register. After 2 clock cycles, delay strobe is generated. Altogether, control unit takes 180 cycles but we have allocated 200 cycles. Hence 20 cycles are left idle.

REFERENCES
[1] “G.726: 40, 32, 24, 16 kbit/s Adaptive Differential Pulse Code Modulation (ADPCM)”, International Telecommunication Union, 1991.
[2] Mark A Indovina, “MCAC I/O internal timing diagram”, EE720, 2014.

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