Superscalar Processor and its Performance issues

686 Words2 Pages

III. THE MICROACRHITECTURE OF A TYPICAL SUPERSCALAR PROCESSOR
Figure 1 represents the microarchitecture of a typical superscalar processor. It includes instruction fetching and branch prediction, decode and register dependence analysis, issue and execution, memory operation analysis and instruction reorders and commit.

A. Instruction fetching and branch prediction
Instruction fetch is done via small and fast memory block known as Instruction cache. The reason for using small and fast memory is to reduce latency. Instruction cache also stores recently executed instructions making the instruction fetch more efficient. All the instructions to be fetched are stored in this memory and are fetched by the program counter. Program counter is used to search the instructions. If the desired instruction is found, then it is termed as cache hit or else it is a cache miss. We all are familiar that superscalar processors execute multiple instructions per cycle. Hence the fetch should be fast enough to fetch multiple instructions from the cache. As a solution to this we separate data cache and instruction cache. Number of instructions fetch should be higher than instructions executed per cycle in order to compensate for cache miss.

Instruction buffer is used to increase instruction fetch efficiency. It holds the number of fetched instructions. If the instruction fetch is stalled; the processor can obtain the instruction via an instruction buffer. In case of sequential instructions, fetching is done by incrementing the program counter by the number of instructions fetched. This value of the program counter is used to fetch the next instructions. In case of non-sequential instructions or branch instructions, fetch should be redirected to fet...

... middle of paper ...

...ming Example [1]
The second method of renaming utilizes a physical register whose size is identical to that of logical registers. This allows one to one mapping between them. In addition to these, it uses a reorder buffer to maintain proper instruction order.

REFERENCES
[1] James E. Smith, Gurindar S. Sohi “The Microarchitecture of Superscalar Processors”, Proceedings of the IEEE, Volume: 83, Issue: 12, pp. 1609-1624, December 1995.
[2] N.D. Shah, Y.H. Shah, H Modi, “Comprehensive Study of the Features, Execution Steps and Microarchitecture of the Superscalar Processors”, IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), pp. 1-4, December 2013.
[3] Steven Wallace, Nader Bagherzadeh, “Performance Issues of a Superscalar Microprocessor”, International Conference on Parallel Processing, Volume: 1, pp. 293-297, August 1994.

Open Document