Many different approaches are used to reduce power consumption at the circuit level design. Some of the main techniques are Transistor Sizing, Voltage Scaling, Voltage Islands, Multiple Threshold Voltages and Power Gating. There is a negative effect with each power optimisation technique used at the expense of performance or area. Rabaey (1996) states that Transistor Sizing (TS) technique is used to adjust the size of each transistor (smallest element in the digital system) or gate (group of transistors)
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a programmable dual-VDD architecture in which the supply voltage of the logic blocks and routing blocks are programmed to reduce power consumption by assigning low-VDD to non-critical paths in the design, while assigning high-VDD to the timing critical paths in the design to meet timing constraints. Evaluation of the effectiveness of different VDD assignment algorithms and architectural implementations show that reducing the supply voltage selectively to the non-critical paths provides significant
consumption of multi-core processors that use the DVFS and CG techniques, while providing the same maximum performance. By scaling the supply voltage (VDD), maximum operating frequency is increased to enhance the performance of a multi core processor. However, increasing VDD is limited by the power and thermal constraints. These constraints can be determined by capacity of supply voltage regulators and cooling solutions in the computing platforms customized for each computing segment. The tuning strategy