Computational Hardware: Random Access Memory

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Random access memory is an essential resource required by the computational hardware. As the processor speed has attained GHz clock frequency, memory throughput can be a bottleneck to achieve high performance. DRAM can deliver a reasonable solution for such data storage. Typical computational system consists of multiple hardware modules that perform different operations on the data. These modules attempt to access the data concurrently. This leads to a requisite for a memory controller that arbitrates amid requests queried by different modules and exploits maximum throughput. The memory controller interfaces DRAM and other subsystems. Hence it manages the data into and out of memory. The access latency or access speed solely depends on the implementation of memory controller. The work concentrates on the relative study of two memory controllers viz., SDRAM and DDR SDRAM controller. The study comprises area, power and timing analysis of the both. Synopsys Design Compiler tool is used to obtain the necessary results.
Index Terms—SDRAM, DDR, ASIC, Latency.
I. INTRODUCTION
Any computational hardware or commonly computer system requires a minimum storage. The storage requirement can be fulfilled by two different classes of memories viz., Static RAM (SRAM) and Dynamic RAM (DRAM). A flip-flop is used in SRAM to retain the information. A single bit SRAM cell is made of 6 transistors and stores the information as a logic level in a cross connection of transistors. Benefits of SRAM are no refresh mechanism, low power consumption and no address multiplexing. Hence making it suitable for higher levels of the memory pyramid where memory must be quick, such as in scratchpads. SRAM has drawback of low memory density and expensive. When there is...

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...ecks and a high on the sys_dly_200us indicates the end of clock stabilization delay. The initialization sequence initiates immediately after the conclusion of clock/power stabilization and then the INIT_FSM will change its state from i_IDLE to i_NOP state. The initialization FSM will switch from the i_NOP state to the i_PRE state on the next clock cycle.
In the i_PRE state, the main control module generates the PRECHARGE command and this command is applied to all the banks in the device. After the PRECHARGE command, INIT_FSM will switch to the next state. The next state in the design of initialization FSM is two AUTO REFRESH commands. These commands will refresh the DRAM memory. After the two refresh cycles, the initialization FSM will shift to i_MRS state. In this state LOAD MODE REGISTER command is generated to configure the SDRAM to a specific mode of operation.

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