Nt1310 Unit 6 Assignment

Jacob Rusgrove
Week 6 Assignment
Grantham University
9-9-17

A bus is a communication system that connects multiple subsystems within a computer. An average computer system normally consists of several components such as a central processing unit, memory devices, and input/output (I/O) devices. The bus system consists of linking media like wires and connectors, and a bus protocol. Buses can be categorized as serial or parallel and synchronous or asynchronous. The bus lets the different components communicate with each other by allowing information to flow between units and devices.
Address lines show the source and end-point of the data on the data lines. Control lines are used in starting the bus protocol. Normally there are lines

These rules are also known as bus protocols. The design of a bus system contains several pro’s and con’s related to the size of the data bus, data transfer size, bus protocols, and clocking. Bus systems are categorized as asynchronous and synchronous buses depending on whether the bus communications are controlled by a clock. There are parallel and serial buses depending on whether the data bits are sent on parallel wires or multiplexed onto one single wire.
When controlling communications of multiple devices are outlined on defined procedures. Arbitration structures are essential in the control of the bus communications in the presence of multiple devices.

In a synchronous bus, the bus system processes are synchronized by way of a clock signal. The bus system clock is provided from the computer system clock, even though it is usually slower than the master clock. Just as an example, 0.6GHz bus systems are used in computer systems with a processor clock of over 5GHz (Matthew, 2004). Bus systems are usually slower than processors. The reason is because memory access times are generally longer than clock cycles of the processor. A bus transaction sometimes takes many clock

Handshaking is done to conduct communication of data between the sender and the receiver. In an asynchronous read operation, the bus system master will set the address and control signals on the bus system. It then declares a synchronization signal. The synchronization signal from the master sets the slave to get synchronized. The reason for this is so that when it has accessed the data, it declares its own synchronization signal. The slave's synchronization signal addresses the processor that there is legal data on the bus, and then it reads the data. This mode of synchronization is known as a full handshake.

A parallel bus system is a bus system that transfers several data bits at the same time. This bus system requires wide buses because large chunks of data need to be transferred faster. Parallel buses usually have 8, 16, 32 or 64 data lines. A parallel bus system includes: ISA, PCI, VESA, and EISA buses. (Mueller, S. & Zacker, C. 1988).
A serial bus system uses the same line to transfer different data bits of the same byte/word. Usually they have only one data line and the bits will flow one after the other, as a packet. An examples of series bus systems are The Universal Standard Bus (USB) and IEEE 1394 bus architecture. Parallel bus systems are more expensive than series bus systems, although, parallel bus systems have a much higher